The JM334D643A-50 is a 32M x 64bits Double Data Rate SDRAM high-density for DDR400.The JM334D643A-50 consists of 8pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 184-pin printed circuit board. The JM334D643A-50 is a Dual In-Line Memory Module and is intended for mounting into 184-pin edge connector sockets. ABDCIGFEH
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features:
-Power supply: VDD: 2.6V ± 0.1V, VDDQ: 2.6V ± 0.1V
-Max clock Freq: 200MHZ.
-Double-data-rate architecture; two data transfers per
clock cycle
-Differential clock inputs (CK and /CK)
-DLL aligns DQ and DQS transition with CK transition
-Auto and Self Refresh 7.8us refresh interval.
-Data I/O transactions on both edge of data strobe.
-Edge aligned data output, center aligned data
-Serial Presence Detect (SPD) with serial EEPROM
-SSTL-2 compatible inputs and outputs.
-MRS cycle with address key programs.
-PCB: 09-2430
-CAS Latency (Access from column address): 2.5
-Burst Length (2,4,8)
-Data Sequence (Sequential & Interleave)
